![]() Moreover, PZT thick films have been deposited on metallic substrates and silicon wafers. 1-3 and 0-3 piezocomposites as well as other highly loaded structures (maximum 45 % in volume) have been elaborated. ![]() With regard to the PZT suspensions formulation, the process was modified to allow the deposition of films with thickness ranging between 8 to 40 μm. In this study, stereolithography of PZT films or composites has been successfully carried out. Some of the drilled holes (diameter about 50 µm) have been successfully filled inside with aluminium by a laser assisted CVD process. bridges and grooves are attainable with widths of 10 micrometers and below. The possibilities of our technology including the creation of holes, channels and three dimensional microstructures will be presented too. In our paper we will show the dependence of the obtained quality especially the roughness of the generated surfaces on the processing parameters. In order to fulfil the industrial demands we have investigated the structuring of anodic bondable PYREX glass and of polymers by means of laser microprocessing using the excimer laser mask projection technique (193 nm wavelength, 10 ns pulse duration, 8 mJ pulse energy, 500 Hz repetition rate). This refers especially to materials that can not or not in a sufficiently quality be processed by conventional methods of silicon technologies. For applications in microsystems technology and biotechnology it is particularly necessary to produce structures with dimensions down to the micrometer scale. Presently, there is a growing demand from the industry for microprocessing of materials. To assure the cover of the different CMOS layers over the step of the islands, it is essential to avoid very sharp steps. The silicon oxide of this SOI region is used as insulator and as sacrificial layer, etched to release the cantilever from the substrate. The CMOS circuitry will be integrated on the bulk silicon region, while the remainder SOI region will be used for the nanoresonator. Starting from a SOI wafer and using very simple processes, the SOI silicon layer is removed, except from the areas in which nano-structures will be fabricated obtaining a silicon substrate with islands with a SOI structure. Prior to the development of this sensor, it is necessary to develop a substrate able to be used first to integrate a standard CMOS circuit and afterwards to fabricate the nano-resonator. For this reason, the control and excitation circuitry has to be integrated on the same substrate than the cantilever. To achieve very high resolution, very small dimensions of the cantilever (nanometer range) are needed. The cantilever is driven electrostatically to its resonance frequency by an electrode placed parallel to the cantilever. This compatibilization is required as first step to fabricate a very high sensitive mass sensor based on a resonant cantilever with nanometer dimensions using the crystal silicon COI layer as the structural layer. The objective of this paper is to present the compatibilization between a standard CMOS on bulk silicon process and the fabrication of nanoelectromechanical systems using Silicon On Insulator (SOI) wafers as substrate.
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |